In selected microprocessors, some of which require high speed registers at local storage, it would be desirable if each register can be separately addressable from the multiplicity of data-in ports for writes and separately addressable to a multiplicity of data-out ports for reads. The data in the register thus would be writable from any data-in port and readable at any data-out port. Such multiport devices might comprise three bit memory configurations arranged with independent read and write addressing so that upon a write the identical information is written into each configuration and the identical address position and then sequential writes will write into the different port addresses in parallel so that each of the three configurations contain the same information and the same address positions. Then a simultaneous read of the three configurations in three different positions with three different addresses-will present three different output words to each of the three different output ports.
Because of reasons which have to do with circuit size, cell ability, wiring density and functional reliability, and performance, present cell arrangements as described in the prior art are not considered applicable. Also they are not readily extendable to multiport configurations greater than three or four ports. For example, as a result of direct design efforts it has been determined that a three port six device cell using read and write memory circuits is almost twice as large as a similarly designed two port differential read and write circuit and that an extension to a five port circuit is totally unreasonable on the basis of size. In addition, the six, i.e., three pairs of differential lines of bit line wires per three port cell becomes ten, i.e., five pairs of differential lines per cell, and this creates significant wireability problems. Thus, such multiport circuits have generally been avoided.
Until the present invention there has been no satisfactory simple cells that can be easily extended to any size multiport configurations as needed nor has such a configuration been developed that will permit simultaneous read and write activities that avoids the time multiplexing of sequential timing schemes of the prior art.